Grazper’s FPGA IP Core has been designed from the bottom up with FPGAs in mind. This means that we take full advantage of their unique structure as compared to GPUs and CPUs. We use our own proprietary techniques for weight and data bit width reduction to take full advantage of the resources on the FPGA. The IP core is written in VHDL and can easily be sized according to the use-case and device.


  • Configurable picture size
  • Sample width: 16 bit integer
  • Weight width: 1 bit/16 bit integer
  • Convolution:
    • Filters sizes: 3x3, 1x1
  • Configurable number of layers
  • Max Pool:
    • Pool region size: 2x2
    • Stride: 0,1
  • Relu and leaky relu
  • Batch Normalization

Please feel free to contact us for further information.